The plurality of interfaces of a non-volatile charge trap memory device, such as an oxide-silicon interface in a semiconductor-oxide-nitride-oxide-semiconductor (SONOS) type structure, are susceptible to dangling bonds forming interface traps. These interface traps readily accept mobile carriers (electrons or holes) causing a variety of problems, such as shifts in the threshold voltage (Vt) of the device or breakdown of an insulator layer, such as a tunneling oxide layer in a SONOS device. In addition, a build-up of mobile carriers may increase the back tunneling current of non-volatile charge trap semiconductor memory cells, thereby dissipating the memory of the stored data more quickly. Consequently, the presence of interface traps may degrade the long-term retention of non-volatile memory cells.
FIG. 1 is a partial cross-sectional view of an intermediate structure for a SONOS semiconductor memory device 10 having a gate stack 28 formed over a substrate 12. In addition, the device 10 typically further includes one or more diffusion regions, such as source and drain regions 26, aligned to the gate stack and separated by a channel region of the substrate 12 below the ONO stack 20. As further shown, device 10 may further include oxide sidewall spacers 24 along the sidewalls of the gate stack 28. Finally, a nitride interlayer dielectric (ILD) 36 may be deposited over the device 10 along with subsequent (ILD) 38.
Briefly, the SONOS gate stack 28 typically includes a poly-silicon (poly) gate layer 22 formed upon and in contact with the ONO stack 20 and thereby separated or electrically isolated from the substrate 12. The ONO stack 20 generally includes a tunnel oxide 14, a charge trapping nitride 16 serving as a memory layer for the device 10 and a blocking oxide 18 overlying the charge trapping nitride 16. In some cases, interface traps within fabricated devices may be passivated such that the build-up of mobile carriers are reduced or eliminated for an amount of time, thereby theoretically improving device reliability. In particular, the dangling bonds within an oxide-silicon interface may be bonded to atomic hydrogen (H) or deuterium (D), removing the interface trap and allowing the device to operate for a longer period of time.
In certain conventionally passivated memory devices, such as that shown in FIG. 1, atomic hydrogen or deuterium may be introduced during an anneal in molecular hydrogen (H2) or deuterium (D2) to passivate interface traps. However, such a conventional technique may present problems affecting the functionality and reliability of the devices. In particular, such anneal processes typically require the use of “pure” hydrogen or deuterium, which is free or substantially absent of other elements. Typically, free hydrogen and free deuterium include safety hazards, which make them difficult to incorporate into semiconductor fabrication processes. Furthermore, the temperature required for deuterium anneals, is typically between 500 degrees Celsius (° C.) and 700° C. Such a high temperature along with a typical annealing duration of between approximately 4 to 5 hours may undesirably increase the thermal budget of an advanced fabrication process, degrading the functionality of device 10. In addition, deuterium cannot readily diffuse through nitride. Consequently, the use of a deuterium anneal in devices, which include nitride layers, such as SONOS devices, are limited in their capability to improve device reliability.
Accordingly, there remains a need to provide a deuterium source to passivate a semiconductor device, such as a SONOS device, in a manner compatible with advanced semiconductor fabrication techniques.